The present invention relates generally to flash memory devices that are electrically programmable and/or erasable, and more particularly, to implanting a predetermined species such as nitrogen such that the predetermined species accumulates at an interface between a bit line junction and a control dielectric structure after a thermal process, for minimizing degradation of such an interface during the program or erase operations of a flash memory device.
Referring to FIG. 1, a cell of a prior art flash memory device 100 includes a control gate 102 which typically is comprised of polysilicon. A first bit line junction 104 that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within a semiconductor substrate 106. A second bit line junction 108 that is doped with the junction dopant is formed within the semiconductor substrate 106.
A control dielectric structure is formed over a control gate area 110 within the semiconductor substrate 106 that is disposed between the first bit line junction 104 and the second bit line junction 108. The control dielectric structure is comprised of a stack of a first dielectric layer 112 disposed on the semiconductor substrate 106, a second dielectric layer 114 disposed on the first dielectric layer 112, and a third dielectric layer 116 disposed on the second dielectric layer 114. In one example of the control dielectric structure, the first dielectric layer 112 is comprised of silicon dioxide (SiO2), the second dielectric layer 114 is comprised of silicon nitride (SiN), and the third dielectric layer 116 is comprised of silicon dioxide (SiO2). A first field oxide 118 is formed within the first bit line junction 104, and a second field oxide 120 is formed within the second bit line junction 108 for electrically isolating the gate dielectric structure comprised of the first, second, and third dielectric layers 112, 114, and 116 and the control gate 102.
During the program or erase operations of the cell of the flash memory device 100 of FIG. 1, charge carriers are injected into or injected out of the second dielectric layer 114. Such variation of the amount of charge carriers within the second dielectric layer 114 alters the threshold voltage of the control gate 102, as known to one of ordinary skill in the art of electronics. For example, when electrons are the charge carriers that are injected into the second dielectric layer 114, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are injected out of the second dielectric layer 114, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the cell of the flash memory device 100, as known to one of ordinary skill in the art of electronics.
The charge carriers are injected into or injected out of the second dielectric layer 114 from the first bit line junction 104 and/or the second bit line junction 108 through the interface between such junctions 104 and/or 108 and the control dielectric structure when bias voltages are applied on the control gate 102 via a control gate terminal 122, as known to one of ordinary skill in the art of electronics. For example, when a bias voltage of approximately +12 V is applied on the control gate terminal 122, electrons are injected into the second dielectric layer 114 from the first bit line junction 104 and/or the second bit line junction 108 through the interface between such junctions 104 and/or 108 and the control dielectric structure by hot carrier injection effect, as known to one of ordinary skill in the art of electronics. Alternatively, when a bias voltage of approximately xe2x88x9212 V is applied on the control gate terminal 122, electrons are injected out of the second dielectric layer 114 and to the first bit line junction 104 and/or the second bit line junction 108 through the interface between such junctions 104 and/or 108 and the control dielectric structure by hot carrier injection effect, as known to one of ordinary skill in the art of electronics.
With such hot carrier injection effect, the charge carriers are injected through the interface between the first bit line junction 104 and the first dielectric layer 112 of the control dielectric structure or through the interface between the second bit line junction 108 and the first dielectric layer 112 of the control dielectric structure. Because charge carriers are injected back and forth through these interfaces in accordance with hot carrier injection effect, such interfaces are prone to develop higher interface defect density with time, as known to one of ordinary skill in the art of electronics. Such interface defects degrade the reliability of the cell of the flash memory device 100 of FIG. 1 because less charge carriers may be injected through such interfaces as higher interface defect density develops with time, as known to one of ordinary skill in the art of electronics.
In addition, with such higher interface defect density, the second dielectric layer 114 may not retain the charge carriers injected therein for a long period of time, as known to one of ordinary skill in the art of electronics. However, if the cell of the flash memory device 100 is part of a static memory device, retention of charge carriers by the second dielectric layer 114 for a relatively long period of time (up to ten years for example) may be the industry standard.
Thus, minimization is desired of interface defect density that may develop from hot carrier injection through the interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device.
Accordingly, in a general aspect of the present invention, a predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device.
A semiconductor wafer having a control dielectric stack thereon is patterned to expose a bit line area and to mask a control gate area of the semiconductor wafer. A junction dopant is implanted into the exposed bit line area to form the bit line junction in the bit line area of the semiconductor wafer. A predetermined species such as nitrogen is also implanted into the exposed bit line area. The control dielectric stack is patterned such that the control dielectric stack is removed from the exposed bit line area and such that the control dielectric stack remains at the control gate area to form the control dielectric structure. A thermal process is performed that heats up the semiconductor wafer. The bit line junction extends under the control dielectric structure from thermal diffusion of the junction dopant to form the interface between the bit line junction and the control dielectric structure. In addition, the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process.
The predetermined species such as nitrogen that is placed towards the interface between the bit line junction and the control dielectric structure minimizes interface defect density and thus degradation of the interface with time during program or erase operations of the flash memory device.
In one embodiment of the present invention, the junction dopant may be implanted into the exposed bit line area at an angle to ensure that the bit line junction extends under the control dielectric structure. In addition, the predetermined species such as nitrogen may be implanted into the exposed bit line area at an angle to ensure that the predetermined species thermally drifts to the interface between the bit line junction and the control dielectric structure.
The present invention may be used to particular advantage when the control dielectric stack is comprised of a first silicon dioxide (SiO2) layer on the semiconductor wafer, a silicon nitride (SiN) layer on the first silicon dioxide (SiO2) layer, and a second silicon dioxide (SiO2) layer on the silicon nitride (SiN) layer, when the junction dopant is comprised of arsenic (As) or phosphorous (P), and when the thermal process is for forming a field oxide at the bit line area to electrically isolate the control dielectric structure.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.